Under the 3G mobile communications network constructions, the developing direction of base stations is how to achieve coverage of the City-intensive wireless network. Currently, the core of network coverage is to set the traditional macro base station apart into two equipments which are Baseband Unit and Radio Remote Unit. The digital transceiver discussed in this thesis is used to Radio Remote Unit in the WCDMA radio base station system, and to realize the transmission of radio signals in mobile communications network.  Digital transceiver is composed of RF treatment,AD/DA transformation, digital up or down converter, interface transformation and Digital optical modules. The focus is to deal with the digital up or down converter. Based on the structure of software radio and FPGA technology, digital up or down converter only be needed to modify parameters in software on the invariable hardware circuits, which could reduce development costs and shorten the research cycle greatly.  According to system design requirements and use comparison of existing chips,this paper selects Altera's FPGA and uses dspbuilder as the system level development tool, Quartus II as the synthesis,place and route tool to design the digital up or down converter.  The main tasks of this paper include the followings:  (1) Based on the analyzing and studying with the overall structure of digital transceiver, the structure of transceiver and functions are determined.  (2) By studying the theory of digital up or down converter, the structure, implementation and performance of digital up or down converter are analyzed.  (3) According to studying with the theory,inner structure and performance about NCO, CIC and FIR filter, specific parameters and simulation structures are proposed.  (4) The IP core in FPGAs is used to the design of digital up or down converter. And using the IP core proposed by dspbuilder in Matlab to finish simulation about NCO, CIC and FIR separately. The whole realizing result of digital up or down converter are achieved in this paper.   (5) Afer researching on the high-speed transmitter and receiver path, the data frame structure is provided based on the system requirements. Stratix II GX which is the Altera's third generation of FPGAs is used to realize serializer, deserializer interface transformation. This is established the foundation for the following-up research work.